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Slave Port Interface
8.4.3
Output interrupt timing
This bit reflects the current state of the INT_O function.
POL
0
0
1
1
INT_O
0
1
0
1
Assertion State
Not asserted
Asserted
Asserted
Not asserted
Table 8-21. Interrupt logic value as a function of the POL bit
Table 8-22. INT_O functional truth table
RESETB
0
1
1
1
1
SET
N/A
Don’t care
WRITE 1
No change
No change
CLR
0
1
0
0
0
Hardware clear
event
N/A
Don’t care
0 1
1
0
INT_O
POL = 0
POL
NOT POL
POL
Previous INT_O
1
Hardware-clear events should never occur at the same time as Write 1 to SET, assuming that the following communication
protocols are followed.
Figure 8-19 on page 139 and Figure 8-20 on page 140 show the I 2 C slave port traffic versus interrupt
assertion and de-assertion for both active high and active low interrupt outputs.
Command
Valid
response
Command
Valid
response
Output interrupt
SP_OIC[INT] = 1
Hardware clears interrupt immediately upon
recognizing a valid response-packet request.
Figure 8-19. Output interrupt timing (POL = 0)
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
139
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